1. Field of the Invention
The present invention relates to a plating apparatus and a plating method, and more particularly to a plating apparatus and a plating method used for filling a fine circuit pattern formed in a substrate, such as a semiconductor substrate, with metal (interconnect material) such as copper so as to form interconnects.
2. Description of the Related Art
Recently, there has been employed a circuit forming method comprising forming fine recesses for interconnects, such as trenches or via holes in a circuit form, in a semiconductor substrate, embedding the fine recesses with copper (interconnect material) by copper plating, and removing a copper layer (plated film) at portions other than the fine recesses by CMP or the like. In this damascene method, from the viewpoint of reducing loads on subsequent CMP, it is desirable that a copper plated film be deposited selectively in trenches or via holes in a circuit form, and that the amount of copper plated film deposited on portions other than the trenches or via holes be small. In order to achieve such an object, there have heretofore been proposed various ideas regarding a plating solution, such as composition in a bath of a plating solution or a brightener used in a plating solution.
A plating apparatus having the following configuration has been known as this type of plating apparatus used for plating to form fine interconnects having high aspect ratios. A substrate is held in such a state that a surface (surface to be plated) of the substrate faces upward (in a face-up manner). A cathode electrode is brought into contact with a peripheral portion of the substrate so that the surface of the substrate serves as a cathode. An anode is disposed above the substrate. While a space between the substrate and the anode is filled with a plating solution, a plating voltage is applied between the substrate (cathode) and the anode to plate a surface (surface to be plated) of a substrate (for example, see Japanese laid-open patent publication No. 2002-506489).
In a plating apparatus in which a substrate is held and plated in single wafer processing while a surface of the substrate faces upward, a distribution of a plating current can be made more uniform over an entire surface of the substrate to improve uniformity of a plated film over the surface of the substrate. Generally, the substrate is transferred and subjected to various processes in such a state that a surface of the substrate faces upward. Accordingly, it is not necessary to turn the substrate at the time of plating.
Meanwhile, in order to deposit a copper plated film selectively in trenches in a circuit form or the like, there has been known a method of bringing a porous member into contact with a substrate such as a semiconductor wafer, and plating the substrate while relatively moving the porous member in a contact direction (for example, see Japanese laid-open patent publication No. 2000-232078).
However, in the prior art, when plating is performed, an amount of plated material is different in regions of the surface of the substrate depending on the shape variations (widths or sizes differences) of the interconnect pattern, such as trenches and via holes, under the influence of distribution of current density or the influence of additives, and hence it is difficult to form a plated film having a uniform thickness over the entire surface of the substrate. For example, a plated film deposited on an interconnect section having a dense fine interconnect pattern (trenches) is thicker than a plated film deposited on other portions, and a phenomenon called an over-plating phenomenon generally occurs. On the other hand, an amount of plated material deposited on an interconnect section having a wide interconnect pattern (trenches) is generally smaller than that on other portions. As a result, in a case where an interconnect pattern is filled entirely with interconnect material such as copper by plating, the thickness of a plated film differs depending on the locations, causing irregularities in the plated film surface. When plating is performed according to such method, more amount of plated material than necessary is deposited, and hence raw material cost increases and a longer period of plating time is required. Further, loads on a polishing process such as CMP after plating increase, and in the next generation in which a low-k material is used as an interlevel dielectric layer, a polishing apparatus will require a considerably high performance.
In order to solve the above problems, various ideas or attempts has been proposed regarding a plating solution such as composition in a bath of the plating solution or a brightener used in a plating solution, and improvement of current condition. These ideas or attempts can achieve the object to a certain extent but have a limitation such as a plated film of poor quality.